module Counter28bit(
	input clk,
	input rst_n,
	output [27:0] Q
);

	wire [27:0] D;
	wire [27:0] Q_internal;

	genvar i;
	generate
		for (i = 0; i < 28; i = i + 1) begin : counter_bits
			MyDFF dff (
				.clk(clk),
				.rst_n(rst_n),
				.D(D[i]),
				.Q_out(Q_internal[i])
			);
		end
	endgenerate

	assign D[0] = ~Q_internal[0];

	genvar j;
	generate
		for (j = 1; j < 28; j = j + 1) begin : d_logic
			assign D[j] = Q_internal[j] ^ &Q_internal[j-1:0];
		end
	endgenerate

	assign Q = Q_internal;

endmodule
